The present invention pertains to the field of digital communication and in particular to demultiplexers for digital signals having two framing sequences.
In digital communications, a signal typically comprises a stream of bits which are all the same. In order to be able to extract information from this digital signal, a transmitter multiplexer inserts identification information into the digital bit stream to provide a frame of reference for a receiver demultiplexer to appropriately group the information bits. This identification information is usually a pre-determined bit sequence which defines a frame. An economical bit sequence is a recurring pattern of a single bit which has an on-off statistic that is highly improbable for any other time slot within the frame. In particular, bits in this pattern recur at regular intervals of "I" bits, where I is the interval from the start of one frame to the start of the next. Such framing is used for the DS1 signal of Digital Telephony where I=193. A further example is the Extended Framing Format of the DS1 signal which has I=772.
Because the bits of a digital signal are all the same, no information can be extracted from a digital signal if framing is not detected. Thus, when framing is lost, communications are lost until framing is re-established. Therefore, a receiver must be sensitive to and recognize the pre-determined framing pattern quickly. Furthermore, framing should be detected with minimal hardware in order to advantageously lower the cost of the entire digital transmission system.
In addition to framing, a further concern of digital system designers is to properly synchronize digital signals emanating from different sources. The bit rate of each such digital signal is established by a sampling clock situated at each terminal equipment. Unfortunately, these sampling clocks are not synchronized. Nevertheless, synchronization can be established by assigning a small fraction of the digital bit stream to the housekeeping function of synchronization. This approach readily allows adding and dropping of digital signals along the transmission route and does not require distribution or derivation of a master clock, or build out of transmission delays.
One technique for using a small portion of the transmitted bit stream capacity for achieving synchronization is known as pulse stuffing. In this technique, the various sampling clocks are allowed to run asynchronously. However, the transmitter multiplexer output rate is set to exceed the maximum possible incoming information rate, i.e. there are a few more bits per second available at the output than can be utilized by the incoming signals. The extra time slots are stuffed with dummy information, and the locations of the stuffed pulses are identified by a synchronization control signal to allow the receiver to delete the stuffed pulses. The receiver removes the stuffed pulses and closes the associated time gaps to deliver a bit stream which is frequency locked and otherwise essentially identical to the input bit stream.
In some instances, the synchronization control signal, also known as stuff indicator bits, can be located by incorporating two framing sequences into a digital signal, each framing sequence comprising a recurring pattern of a single bit. The stuff indicator bits, which indicate the presence or absence of stuffed pulses, are offset at specified positions from the bits of the framing sequences.
Both the DS1C and the DS2 digital signal formats used in Digital Telephony utilize two framing sequences in the manner described hereinabove. The bits of the first framing sequence recur every I bits in the digital signal and the bits of the second framing sequence recur every N.times.I bits, where N is an integer. The bits of the second framing sequence are displaced from the bits of the first framing sequence by D bits and occur 1/N as often in the digital signal as do the bits of the first framing sequence. The second framing sequence is used to locate the stuff indicator bits. For the DS1C digital signal, D=53, I=159 and N=2; and for the DS2 digital signal, D=49, I=147 and N=2.
Tables I and II illustrate the DS1C and DS2 signal formats, respectively. Control bits labelled "F" are framing bits for the first sequence. Control bits labelled "M" and "C" appear between the "F" bits. The "M" bits are framing bits for the second framing sequence and the "C" bits form the three bit code which denotes the presence or absence of a single stuffed pulse. Redundant coding is used to protect the stuff indicator signal against errors. Three to one redundancy with majority vote at the receiver protects against single errors. The brackets with number contained therein indicate the location of the information bits, the numbers within the brackets indicating the number of information bits. In Tables I and II, the subscripts of the "M" and "F" bits identify the bit as a "0" or a "1".
TABLE I ______________________________________ DS1C (3.152 Mb/s) Digital Signal Format ______________________________________ M.sub.0 [52] C.sub.1 [52] F.sub.0 [52] C.sub.1 [52] C.sub.1 [52] F.sub.1 [52] M.sub.1 [52] C.sub.2 [52] F.sub.0 [52] C.sub.2 [52] C.sub.2 [52] F.sub.1 [52] M.sub.1 [52] C.sub.1 [52] F.sub.0 [52] C.sub.1 [52] C.sub.1 [52] F.sub.1 [52] M.sub.x [52] C.sub.2 [52] F.sub.0 [52] C.sub.2 [52] C.sub.2 [52] F.sub.1 [52] ______________________________________
Table I illustrates the format of the DS1C signal. The DS1C signal is formed as follows: two DS1 Digital Telephony standard 1.544 Mb/s signals are input to a transmitter multiplexer as bipolar signals; each DS1 signal is converted to the unipolar signal format; the second DS1 signal is logically inverted, i.e. all "0"s are converted to "1"s and all "1"s are converted to "0"s, to control the signal statistics of the DS1C signal; each DS1 signal is stuffed; the DS1 signals are multiplexed by interleaving them bit-by-bit; the interleaved bit stream is scrambled according to a scramble algorithm where each scrambler output bit is the modulo two sum of the corresponding input bit and the preceding output bit; the scrambled signal is combined with the "F", "M", and "C" control bits; and, finally, the resultant signal is converted to a bipolar format having a 50-percent duty cycle for transmission.
Each control bit precedes a block of 52 bits from the multiplexed DS1 signals, 26 bits from each, indicated by [52] in Table I. The control bits form a 24-bit long repetitive sequence, which, with the 52 information bits associated with each control bit, defines a 1272-bit block called an "M" frame. This 24-bit control bit sequence may be regarded as a digital word, the individual bits of which are dispersed in the composite signal bit stream. The sequence of "M" bits, i.e. the second framing sequence, consists of four bits designated M.sub.0, M.sub.1, M.sub.1, and M.sub.x. They are the first, seventh, thirteenth, and ninteenth bits in the 24-bit sequence of control bits and define the start of four 318-bit subframes in the 1272-bit "M" frame. The first three of the "M" bits, "0 1 1", are used to identify the "M" frame and the fourth bit, x, is used for maintenance signaling. A "1" indicates no alarm and a "0" indicates the presence of an alarm.
The "F" bit sequence, i.e. the first framing sequence, is made up of alternate "1"s and "0"s that appear at the beginning of every third 52-bit information sequence, i.e., as every third bit in the 24-bit control bit sequence.
There is a sequence of three "C" bits in each subframe, three "1"s for the presence of a stuff bit and three "0"s for nostuff. The locations of the "C" bits is established from the M.sub.0 M.sub.1 M.sub.1 M.sub.x second framing sequence. The stuffed bit is the fifth information bit following the third "C" bit in a subframe for the first DS1 signal and the sixth information bit following the third "C" bit in a subframe for the second DS1 signal. In Table I, C.sub.1 denotes stuffing indicator bits for the first DS1 signal and C.sub.2 denotes stuffing indicator bits for the second DS1 signal.
______________________________________ DS2 (6.312 Mb/s) Digital Signal Format ______________________________________ M.sub.0 [48] C.sub.1 [48] F.sub.0 [48] C.sub.1 [48] C.sub.1 [48] F.sub.1 [48] M.sub.1 [48] C.sub.2 [48] F.sub.0 [48] C.sub.2 [48] C.sub.2 [48] F.sub.1 [48] M.sub.1 [48] C.sub.3 [48] F.sub.0 [48] C.sub.3 [48] C.sub.3 [48] F.sub.1 [48] M.sub.x [48] C.sub.4 [48] F.sub.0 [48] C.sub.4 [48] C.sub.4 [48] F.sub.1 [48] ______________________________________
Table II illustrates the format of the DS2 signal. The DS2 signal is made up of a combination of four DS1 signals. A 24-bit control bit sequence, along with 48 information bits associated with each control bit, defines an 1176-bit "M" frame which is divided into four 294-bit subframes. The "M" and "F" bit sequences are the same as described hereinabove for the DS1C signal. Each control bit is followed by a 48-bit block of information of which 12 bits are taken from each of the four DS1 signals. They are interleaved sequentially in the 48-bit block. The stuff indicator bits, i.e. "C" bits, use the same code as described hereinabove for the DS1C signal and are transmitted at the beginning of the 2nd, 4th, and 5th 48-bit information blocks within each subframe. The stuff bit positions are all assigned to the sixth 48-bit information block in each subframe. In subframe No. 1, the stuff bit is the first bit after the F1 bit; in subframe No. 2, the stuff bit is the second bit after the F1 bit, and so on through the fourth subframe. In Table II, C.sub.1 denotes stuffing indicator bits for the first DS1 signal, C.sub.2 denotes stuffing indicator bits for the second DS1 signal, and so forth.
Prior to multiplexing, input DS1 signals 2 and 4 are logically inverted to improve the properties of the output DS2 signal. At the output of the multiplexer, the signal is converted to a bipolar format having a 50-percent duty cycle. The format used is called "bipolar with six-zero substitution."